1. Field of the Invention
The present invention relates to a static random access memory (SRAM) control circuit and, more particularly, to an SRAM control circuit with a power saving function.
2. Description of Related Art
In general, memory can be divided into two types, SRAM and DRAM (dynamic access memory). Upon the same chip area, DRAM normally is more than four times the capability of SRAM but SRAM is more than four times the speed of DRAM. In addition, SRAM costs much higher and consumes more power than DRAM. Therefore, for the balance between memory price and performance in computer design, SRAM for use as a cache memory is generally provided between the central processing unit (CPU) and DRAM, thereby providing a cache function.
FIG. 1 is a schematic diagram of a typical SRAM structure. As shown in FIG. 1, an address decoder 10 reads and decodes data on address lines in order to output an address signal to select a specific memory area in a memory unit 14. A chip select signal ˜CS enables the memory unit 14 to be read/written in the special memory area. When the chip select signal ˜CS and an output enable signal ˜OE are active, the memory unit 14 is active to read, and thus data stored in the specific memory area is outputted to an external circuit after being buffered by a buffer 18. When the chip select signal ˜CS and a write enable signal ˜WE are active, the memory unit 14 is active to write, and thus data inputted by the external circuit to the buffer 18 is written in the specific memory area. All the chip enable signal, the output enable signal and the write enable signal employ the low active mode; i.e., they are active at low level and inactive at high level.
However, in recent years, portable devices are in wide spread use, which require not only the operating speed but also low power consumption. In an example of a general SRAM chip, the entire SRAM chip requires 2 μA at a standby mode while requiring 20 μA at an operating mode (during read/write data, namely, chip enable signal at low level). Accordingly, power consumption difference between the two states can be 10,000 times. Therefore, high power consumption in typical SRAM memory can be further improved. Therefore, it is desirable to provide an improved SRAM control circuit to mitigate and/or obviate the aforementioned problems.